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Dynamic, On-Chip Power Supply Grids

On-Chip Supply GridsMixed-signal SoCs include a large number of diverse system sub-components that are integrated together in a single nanometer CMOS chip, with each sub-components typically requiring its own independent, and well-isolated power supply. Moreover, with the diminishing returns of technology scaling and low-power circuit design in terms of reducing power consumption, the industry is moving away from using static power supply levels and adopting instead a dynamic approach. In such approach, the power supplies are dynamically adapted based on the real-time demand of the sub-components in order to better manage and reduce the overall power consumption of the system. This approach can be applied, in theory, at any granularity where each sub-component is further divided into yet smaller sub-components with their own separate power supplies. Therefore, as SoCs grow further, the number of independent power supplies needed in the system becomes very large, and implementing them in a size- and cost-effective manner becomes very challenging. This is mainly due to the fact that conventional power supplies require high quality passive components that often can’t be integrated on chip, and thus the Bill of Material (BOM), package pin count of the SoC, and Printed Circuit Board (PCB) area become prohibitively large and costly. Moreover, as dynamic powering becomes more dominant, these power supplies need to have fast dynamic performance, which traditionally comes at the expense of much degraded power conversion efficiency.

The focus of this research is to address the above challenges by developing new power supply architectures that enable the implementation of a large number of highly dynamic and efficient on-chip power supplies, i.e. on-chip power supply grids.

Related Publications:

  1. S. Asar, H. Zhang, and A. Fayed, “Dual-Frequency SIMO Topologies for On-Chip Dynamic Power Supplies,” 2018 IEEE Power Supply on Chip Workshop (PWRSoC), Hsinchu, Taiwan, Oct. 2018. Poster.

  2. Yongjie Jiang and Ayman Fayed, “A 1A, Dual-Inductor 4-Output Buck Converter with 20-MHz/100-MHz Dual-Frequency Switching and Integrated Output Filters in 65nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2485-2500, Oct. 2016.

  3. Chih-Wei Chen and Ayman Fayed, “A Low-Power Dual-Frequency SIMO Buck Converter Topology with Fully-Integrated Outputs and Fast Dynamic Operation in 45-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2161-2173, Sept. 2015.

  4. Chih-Wei Chen, Jeffrey Morroni, David Anderson, and Ayman Fayed, “Dual-Frequency SIMO Power Converters for Low-Power on-Chip Power Grids in SoCs,” 2014 IEEE Applied Power Electronics Conference (APEC), Fort Worth, Texas, Mar. 2014, pp. 1954-1957.

  5. Yongjie Jiang and Ayman Fayed, “A 1A, 20MHz/100MHz Dual-Inductor 4-Output Buck Converter with Fully-Integrated Bond-Wire-Based Output Filters for Ripple Reduction,” 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, Sept. 2015, pp. 1-4.

  6. Wei Fu and Ayman Fayed, “Power Conversion Schemes in Mixed-Signal SoCs,” 2014 IEEE Int. symposium on circuits and Systems (ISCAS), Melbourne VIC, Australia, Jun. 2014, pp. 606-609.