Sita and Hua's Poster to be Presented in the 2018 IEEE PWRSOC
Congratulations to Sita Asar and Hua Zhang for the acceptance of their poster entitled "Dual-Frequency SIMO Topologies for On-Chip Dynamic Power Supplies," in the 2018 IEEE Power Supply on Chip Workshop (PWRSoC), Hsinchu, Taiwan, Oct. 2018.
The Dual-Frequency Single-Inductor Multiple-Output (DF-SIMO) buck converter topology with freewheeling control is a promising approach for enabling the implementation of multiple efficient on-chip power supplies with superior dynamic and cross-regulation performance. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency reduces the required output capacitors to levels where they can be implemented on-chip, and results in superior dynamic performance and cross-regulation behavior without the significant efficiency loss and design complexity that would result from switching both the input and output stages at high frequency. Targeting multi-core CPUs and System-on-Chip (SoCs) with multiple power domains in nanometer CMOS, the DF-SIMO topology can be implemented in various ways based on the number of required outputs, power levels, and ripple voltage. This poster presents a 2-MHz/120-MHz design in 45-nm with 110mA total output current and 5 on-chip outputs, and a 20-MHz/120-MHz design in 65-nm with 1A total output current and 4 on-chip outputs.