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Yongjie's Paper Appears in IEEE JSSC

Yongjie JiangCongratulations to Yongjie Jiang for the publication of his paper entitled "A 1A, Dual-Inductor 4-Output Buck Converter with 20-MHz/100-MHz Dual-Frequency Switching and Integrated Output Filters in 65nm CMOS" in the IEEE Journal of Solid-State Circuits. The paper was #11 out of the top 50 most popular papers in IEEE JSSC in the month of October, 2016.

In this paper, the Dual-Frequency Dual-Inductor Multiple-Output (DF-DIMO) buck converter topology is proposed. The topology employs a dual-phase 20-MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-outputs 100-MHz comparator-controlled fully-integrated output stage to reduce the capacitance required per output to 10 nF. In order to enable each output to handle up to 250-mA load with less than 40-mV voltage ripple, a 3rd-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency and dynamic performance, and high-gain error amplifier in the output feedback loop to enhance DC load Regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65-nm CMOS technology with 1.8-V input, and outputs in the range of 0.6–1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40-mV output voltage ripple, 0.5-V/70-ns Dynamic Voltage Scaling (DVS), and settling time of less than 85 ns for 125-mA load steps; all with no observable cross regulation transients.